8 Aug
2025
8 Aug
'25
9:54 a.m.
On Thu, 7 Aug 2025, Paul Koning wrote:
Pipeline interlocks removed delay slots; by that time the MIPS ISA got
rid of some of them already as well, as people quickly realised they were
not the best idea (the most recent MIPS ISA revision is I believe fully
interlocked). Then MIPS unaligned memory access instructions (LWL/LWR,
SWL/SWR, etc.) were covered by a patent, so naturally DEC wanted to avoid
them and came up with a different approach. There was also the notable
lack of byte and word memory access instructions in the initial ISA. I
find all these minor ISA design decisions though.
The key concepts clearly borrowed from the MIPS ISA were: a hardwired
zero register and the dependency on that for the completeness of the ALU
operations provided, the lack of condition codes and the use of general
registers instead for conditional branches, and the overall feel of the
instruction set, including but not limited to the 6-bit major opcode
encoded in bits 31:26 of the instruction word and the placement of the
5-bit register operand fields.
Maciej
>> I
believe the ancestry of Alpha is a bit different, given that it was
>> DEC's third generation RISC design, after the R&D one-off Titan (1982,
>> see https://bitsavers.org/pdf/dec/tech_reports/WRL-86-1.pdf) and the
>> canceled PRISM (spring 1985,
>> https://bitsavers.org/pdf/dec/prism/memos/850528_NONVAX.pdf which
>> mentions Titan and Berkeley but not MIPS as inspiration).
>
> Well, the similarity of the ISA is striking, unlike with say the ARM or
> POWER ISAs, and the timeline and the use of MIPS processors in DEC systems
> makes it hard to believe there was no influence. That does not preclude
> other inspirations and it's worth noting that a key architectural mistake
> was avoided (learnt from?), that is the lack of pipeline interlocking.
I don't think of them as all that similar, apart from the inherent
similarity of RISC architectures generally. For example, it avoided the
horrors of the delay slot. And it had some odd decisions, like the
initial lack of unaligned load/store and the omission of the divide
instruction.