22 Sep
2025
22 Sep
'25
6:47 a.m.
Yes, that is a very good point. With long running APL and BASIC code,
execution traces show instructions from an executable language ROS,
interleaved with ExecROS. I have the impression that they system was
designed so all language ROS paths "come up for air" in ExecROS
periodically.
But I agree that there are cases such as tape or disk that could need to
avoid holding off interrupts. Could be that just holding off level 3 is
enough.
Before gating the interrupt I would watch traces where the first HOLD
went through your (nicely annotated) ExecROS code and correctly got to
the HALT. But if the code had not been running from ExecROS, a
subsequent HOLD intended to resume execution instead wandered around
executing until it hit a 0x000 and halted.
There were many visible symptoms such as random bits of unrelated error
messages or parts of the screen changing, all making me feel that the
instruction counter was in the wrong bank and basically just lost.
Since adding if(curr_ros==ExecROS) that's resolved.
Robert
On 9/22/25 1:55 AM, Christian Corti via cctalk wrote:
On Fri, 19 Sep 2025, Robert Marinelli wrote:
So looking through the pseudo-schematics/block
diagrams in
SY31-0552-3 IBM 5110 System Logic there is quite a bit of gate logic
on the multiple ROS cards, plenty of wires between them. Maybe,
hardware interrupts are held off in hardware when we are doing reads
from the language ROS cards. The interrupt bits are properly shown
in a register, but nothing detailing gating of interrupt -> CPU.
Hm, this is a very good point! Actually, thinking about it, the system
ISRs are located in the ExecROS (e.g. keyboard ISR), so you may be
correct about "ANDing" the interrupt line with the ExecROS select
line, *if* the interrupt mode bit for that level (i.e. 0-3) says that
the ISR is in a ROS. On the other hand, you can have an ISR in RWS, so
that could be called anytime.
To test the idea I made this change in emu.c:
175c175,176
< check_int(); /* check for pending interrupts */
---
This may break an ISR in RWS, but I haven't tested this with your
modification.
Christian if(curr_ros==ExecROS) /* if in ExecROS we can
HOLD/resume */
> check_int(); /* check for pending interrupts */