8 Aug
2025
8 Aug
'25
10:52 a.m.
On Aug 8, 2025, at 1:30 PM, ben via cctalk
<cctalk(a)classiccmp.org> wrote:
On 2025-08-08 10:54 a.m., Maciej W. Rozycki via cctalk wrote:
The same thing as branch on register? Nope, "skip on condition" is a flavor of
condition code branch. The RISC argument against condition codes, and why Cray didn't
use them in the 6600, is that they are an instruction side effect that has to be
interlocked along with the "real" result. And it's a global state, so it
introduces unwanted serialization.
For example, in a 6600 (or a MIPS or an Alpha), you can have an add into R3 executing
concurrently with a multiply into R4, with no output conflicts. If you add condition
codes to the architecture, those are a second output and the two operations now conflict.
Another advantage is that you can conditionally branch on a result from some number of
instructions ago, while instructions in between are still finishing up. No need to drain
the pipeline. Of course there are other ways to do the "some instructions ago"
thing, by having condition codes that are set only if an instruction option says to do so.
The Electrologica machines (X1, from 1958, and the successor X8) have that feature, making
them similar to ARM but more flexible.
On Thu, 7 Aug 2025, Paul Koning wrote:
The key concepts clearly borrowed from the MIPS
ISA were: a hardwired
zero register and the dependency on that for the completeness of the ALU
operations provided, the lack of condition codes and the use of general
registers instead for conditional branches..
Funny how most classic computers, did the same thing.
It was called skip on condition. With out the advance of large fast paged DRAM's
RISC would
never got out the Door.
The 6600 max memory was 128k 60-bit words, which for those days was admittedly quite
large. No VM, though it did support relocation (base address and field length, similar to
the DEC KA10). Large RAM is nice but I don't see what it has to do with RISC.
paul