test-drb August 2009

test-drb@ccmp.vtda.org

148 participants
169 discussions

by tsw-cc＠johana.com

I found one on EBAY that looks like it may go for a song. If you get it, I have done an interface for a parallel printer port. It works without kernel software modification (assuming you use plain text) on Linux where I've used it. Ebay info: Facit Paper Tape Punch Model 4070 (290335224061). My interest is not in the punch, but I'm willing to supply the interface (it isn't that big). What I'm after is the plastic chad box as I don't have one, and a plastic baggie is a poor substitute (*SIGH*).

17 years

DENCON

by ajp166＠bellatlantic.net

> >Subject: Re: DENCON > From: Ethan Dicks <ethan.dicks at gmail.com> > Date: Mon, 10 Aug 2009 22:02:23 -0400 > To: "General Discussion: On-Topic and Off-Topic Posts" <cctalk at classiccmp.org> > >On 8/10/09, Brent Hilpert <hilpert at cs.ubc.ca> wrote: >> Jim Leonard wrote: >>> >>> A PDP-11 gets some love: http://ascii.textfiles.com/archives/2114 >> >> Wow. That's a rather, umm, unique combination of machinery and carpet, but >> somehow they work together. Sort of. > >I was thinking more that the panoply of machinery was straight out of >one of DECs handbooks, but on garishly "modern" (by comparison) >carpet. > >I couldn't tell from the photos - is that an HSC50 on the far right, >or if not, what? > >-ethan I'd offer that it looks like a VAX/750 and two disk/tape racks. There appear to be several systems there with the -11 being the featured one. Allison

17 years

UNIBUS <-> PCI bridge

by bqt＠softjar.se

Roger Ivie <rivie at ridgenet.net> wrote: > On Mon, 10 Aug 2009, Johnny Billquist wrote: >> Roger Ivie <rivie at ridgenet.net> wrote: >> Second, the vector transfer isn't a normal bus transfer in the sense of the >> device addressing the CPU and transferring a word. > > Page 2-13 of the UNIBUS spec (1979): "INTR is a bus signal asserted by > an interrupting device *after it becomes bus master* to inform the > interrupt fielding processor that an interrupt is to be performed and > that the interrupt vector is present on the D lines." > > Technically, you don't even have an interrupt until the device hands you > the vector. Which it does as a bus master. Ah. Yes, I see now (or remember). INTR is a bus transaction, with the interrupt fielding processor as the implicit slave. >> The CPU cannot be a slave, >> unless my memory fails me. > > Page 2-14: "INTR is negated upon receipt of the assertion of SSYN from > the interrupt fielding processor." I was just remembering the DATI/DATIP/DATO/DATOB transactions, which can't address the CPU. I didn't remember that the vector transfer had it's own operation on the bus. Nice design really. Yes, once your bus request is granted, you can do anything on the bus. >> It's been way many years since I looked at the unibus map of the VAX UBA, but >> I can't for my life imagine that it could be any simpler than the Unibus map >> of the PDP-11. > > The PDP-11 can map a UNIBUS page to any *word boundary* in the memory > space. That means there are adders in there somewhere. The VAX > scatter/gather map just replaces bits 9 and up with the contents of the > map entry. Having an adder, or an or with a mask, isn't much different, or conceptually any more complex in my eye. But maybe that is just me. :-) Johnny -- Johnny Billquist || "I'm on a bus || on a psychedelic trip email: bqt at softjar.se || Reading murder books pdp is alive! || tryin' to stay hip" - B. Idol

17 years

Classic computer classifieds anywhere?

by alanp＠snowmoose.com

As previously noted, I have been thinning my collection. Rather than filling this list with updates, are there classic computer classifieds where I can just post a list of stuff that is available and then add and subtract items from the ad as appropriate? alan

17 years

Results from a pickup today...

by ken＠seefried.com

> Venix would be awesome to try out... I had used > their 386 variant in days long past. Fair warning...the Pro/350 version of Venix is about as much like the i386 version as 2BSD is like 4BSD. KJ

17 years

ASR-33 original price?

by evan＠snarc.net

Does anyone know the (approximate) original prices for the ASR-33 and KSR-33?

17 years

[rescue] Tapes, Drives, Libraries, and Arrays Need to Go (fwd)

by dgriffi＠cs.csubak.edu

If someone would forward this to CC-talk and elsewhere, I'd appreciate it. I am preparing to move soon. I don't know how soon, but it's likely going to be the case that I find something in a neighborhood I want, that I can afford, and that I need to pounce on quickly, so I'm trying to be rid of anything I don't have any hope of ever using. I have a huge cabinet (I think it holds either 300 or 500 reels) of full of 2400ft nine track tapes. I no-longer have a working nine-track drive. This cabinet is about four feet wide, seven feet tall, and two feet deep. This pile o' tapes, the cabinet in which they hang so uselessly, and the non-working DEC SCSI tape drive[0] need to go. I don't want any cash for it or the tapes, just please come and get them. If you only want the drive, I'll deliver it anywhere in Austin, but preference will go to someone who'll pick up the cabinet full of tapes. I also have a Sun StorEdge L3500 tape library with six DLT7000 drives. It is mechanically sound, and the drives work, but there's a defective optointerruptor that determines the X position of the carriage; it's a cheap part to replace and shouldn't take a lot of labor, but I'm backing up to disk now. You may either pick this up, or help me load it and unload it, and I'll drive it to your central Texas location with my truck. Photos of the library are here: http://jonathan.celestrion.net/photos/library/ I also have a Compaq Storageworks BA370 24-slot enclosure with dual controllers. This takes SCSI Storageworks "storage building blocks", and I may actually have enough of them to fill the unit (not necessarily with disks in the blocks). I have spare batteries, controllers, and other bits. Need a fiber switch? I have gigabit Brocade Silkworm and possibly enough GBICs to fill it. Feel free to make an offer on the BA370 or the switch. I'll mail the switch or deliver the BA370 in central Texas, but I won't ship the BA370 anywhere; it's just too hard to crate reasonably. [0] I don't recall the model, but it's vacuum-loading, SCSI, and 5 or 6 rack units tall. The failure mode is that it fails to load the tape (or loads, fails to notice, and then unloads), so hopefully it's just a sticky sensor. -- Jonathan Patschke ( "They don't have the right to read a book out loud." Elgin, TX ( --Paul Aiken USA ( Executive Director, Authors Guild _______________________________________________ rescue list - http://www.sunhelp.org/mailman/listinfo/rescue

17 years

Commodore 1526 ribbons?

by evan＠snarc.net

Can anyone recommend a source for new Commodore 1526 ribbons? Only place I found online is http://www.ocla.com/makepagebak8.php?SUBCAT2B=COMMODORERIBBONS .... hoping that someone here can vouch for that business, or (better yet) direct me toward a lower price.

17 years

UNIBUS <-> PCI bridge

by bqt＠softjar.se

Roger Ivie <rivie at ridgenet.net> wrote: > On Fri, 7 Aug 2009, Johnny Billquist wrote: >> > Interrupt stuff is usually a bit more complicated than what you seem to >> > envision above. You have the interrupt request line, the interrupt grants, >> > which is followed by the vector at the interrupt acknowledge, and then you >> > have the interrupt dismiss stuff, which cause the device to remove the >> > interrupt request, and allow other devices at the same priority, but farther >> > from the bus arbiter to get their interrupt through. > > Interrupts are actually a bit odd on the UNIBUS, where interrupt > requests are really just prioritized DMA requests. A UNIBUS device > asserts a bus request and gets a bus grant, at which point it may do > *any* kind of bus traffic. Providing a vector to the computer is just a > specialized kind of DMA write; one with an implied address, as it were. Hmm. Now I'm just writing from memory, which sometimes is a really big mistake, but I don't think that is correct. First of all, interrupt bus requests are only granted at instruction fetch time, while DMA bus requests can be granted at any stage of the CPU execution cycle. Second, the vector transfer isn't a normal bus transfer in the sense of the device addressing the CPU and transferring a word. The CPU cannot be a slave, unless my memory fails me. However, at the interrupt acknowledge cycle, the device is expected to put out the vector, and the CPU will read the data in from the bus and gate it into temporary storage, followed by pushing the PSW and PC, and reading a new PSW and PC from the address given by the vector. This is a rather complex behaviour, and not something you can manage to trick the CPU into doing under any other circumstances. As for asserting the interrupt request, and getting a bus grant in return, that is pretty much how all CPUs work. The big difference is only in what they call the signal, and how the device is expected to behave once the grant comes in. Many CPUs have just a single interrupt request line, and a single interrupt acknowledge line. The fact that the Unibus defines four is nice, though. :-) > It's been a few years, time kills brain cells, yadda yadda yadda, but I > did actually design a UNIBUS processor board once upon a time. With a > UNIBUS map. The PDP-11 UNIBUS map is not as simple as the one used on the > VAX. It's been way many years since I looked at the unibus map of the VAX UBA, but I can't for my life imagine that it could be any simpler than the Unibus map of the PDP-11. But maybe that's just me. :-) Johnny -- Johnny Billquist || "I'm on a bus || on a psychedelic trip email: bqt at softjar.se || Reading murder books pdp is alive! || tryin' to stay hip" - B. Idol

17 years

Results from a pickup today...

by ken＠seefried.com

You can also run Venix 2.x on a Pro/350, and I think there are images floating around. It's System III based with real-time extentions. Not a bad system for the time. Interesting contrast to 2BSD. KJ

17 years

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test-drb August 2009