17 Nov
2011
17 Nov
'11
7:24 a.m.
On 17 Nov 2011 at 8:05, Brad Parker wrote:
I'm not sure why you are saying this. You
don't need a clock to
implement combinatorial logic in a CPLD, or a FPGA.
There's nothing stopping you from taking two inputs, anding them
together and putting the output on another pin.
The clock give the software a reference for timing analysis. But it's
not required.
Thanks for that information--I'll have to go back and revisit some of
my old code and see exactly what it was that was the stumbling block.
One that I recall was a peripheral interface that did little other
than propagate and switch signals. The error messages that I was
getting made me relent and add synchronizers for a fully-clocked
design. It worked, but I always wondered why that was necessary,
seeing that I could do the same thing without a clock and a board of
TTL.
Thanks,
Chuck