On 7/27/10, Charlie Carothers <csquared3 at
tx.rr.com> wrote:
  Tony Duell wrote:
  All decent buses allow you to share interrupts --
the ''design' of the
 interrupt suystem on the ISA bus is one reason to hate that bus..
 Very well designed buses (Unibus :-)) have each card send an interrupt
 vector which directs the CPU to the right ISR. 
 ... I'm just curious as to how
each card knows  what interrupt
 vector value to send?  Jumpers/switches on each card? 
 Can be done that way...
  A "Unibus Interrupt Vector Value Guru"
somewhere who assigns the values? 
 In a sense, yes....
 All the way back to 1970, DEC published lists in various system
 handbooks about their own breakdown of assigned CSRs (Control Status
 Register - typically the first I/O address that the card responds do,
 though there's no way to magically know how many addresses a card will
 answer at) an interrupt vectors for disk controllers, comms
 controllers, etc.  For older devices, DEC would reserve up to four
 locations for a given interface, allowing for primary through
 quaternary cards to be installed on the same bus.  Later, there was
 typically a primary address given, then a scheme to calculate a
 non-conflicting "floating" address, but by then folks were rarely
 installing four of anything except perhaps serial interfaces or MSCP
 disk interfaces.
 I can give an example of how this worked in practice by describing a
 3rd-party device I used to make and maintain, the COMBOARD.  It wasn't
 on DEC's list, so we picked an arbitrary CSR up in "unassigned" space.
  We gave our customers a list of eight preferred CSR addresses to use,
 though any address in the I/O page would work.  The user set the CSR
 address on a 10-position DIP switch, then, once the machine was
 powered on and running, would load the driver and tell it, via setup
 files, what CSR the card(s) will respond at.  Our product had a 16-bit
 double-one-way register we called "the window".  If the PDP-11/VAX
 wrote a value, the 68000 on the card could read it, and if the 68000
 wrote a value, the PDP-11/VAX could read it (a processor could never
 read back the value that it just wrote).  One of the values passed
 during initialization was the vector to use (as stated in a config
 file that was written by the user, or by us as a factory default).
 The board would retain that value and drop it on the bus during an
 interrupt request.
 So for our product, the CSR was set by switches that were not meant to
 be changed, but the interrupt vector could be changed at every reboot.
  Real DEC devices did a number of different things, the older ones
 typically relying on jumpers or switches, the newer devices relying on
 some mechanism to assign or calculate the values dynamically.
 In practice, there weren't as many kinds of interfaces for the Unibus
 as there ended up being for the ISA bus, so it may sound like anarchy,
 but it wasn't.  I think in 20-ish years of the hey-day of the Unibus,
 they only ever reassigned CSR addresses once or twice, but it was
 extremely unlikely that you'd have a particular obscure peripheral
 from 1970, literally, on the same bus as a stack of c. 1990 disk
 controllers and Ethernet interfaces.  Electrically, they would work
 together, but logically, a user would have no need to use 20-year-old
 devices.  The only "old" device we ever used on our VAX-11/750 was an
 LP11, an original line-printer interface.  The rest of the cards in
 our machine were manufactured 10-15 years later.  Some of our devices,
 then, had a DIP switch for CSR assignment, but not for vector
 assignment.  Something older, like a PDP-11/34, was probably a
 different story.
 -ethan
  
That's quite interesting, thanks.  Since I never had the privilege of
working with DEC gear during my career, it's nice to pick up a few
tidbits here and there, mostly by reading this group.  I can see where
the main CPU being able to configure the controller board could provide
a lot of flexibility.
BTW, with a 68000 on board I would imagine that your COMBOARD product
was a rather intelligent I/O interface!
Later,
Charlie C.