5 Mar
2008
5 Mar
'08
11:14 a.m.
From: ard at p850ug1.demon.co.uk (Tony Duell)
Subject: Logic testing
I fail to see what silicon .vs. germanium has to d owith the
polarity of
the logic cignals. In general PNP transistors, and for that matter
PMOS
fets, imply -ve logic levels, and plenty of machines were built using
those components. Also ECL chips have -ve logic levels (around -2V)
wrt
ground.
I bow to your greater knowledge. I was employed as a programmer and
picked up hardware later.
The HP Logicdart (a handheld 3-input logic analyser) can certainly
handle
the PMOS logic signals in older HP handheld calculaotrs and the -15V
logic levels in the discrete transistor circuitry of the HP9100. I
don't
see why it'd not work for you. And most _decent_ logic analysers (as
opposed to the TTL-only toys...) can handle ECL levels.
In cany case, I cna't believe the signals in your machine are all that
fast. Is it not possible to make up level shifter stages to turn them
into TTL-level sgiansl for testing?
Indeed, the clock is 1MHz, 750ns high and 250ns low, with lots of
wobbling about as the signal overshoots.
Thanks Tony, if I see a logic analyser going cheap (though that is
unlikely) I will buy it.