16 Nov
2011
16 Nov
'11
11:23 a.m.
Well. Technically, you CAN run an FPGA or CPLD
completely
combinationally [...]. However, it drives the timing closure engines
completely nuts because they're designed to analyze synchronous
designs.
Ah, so the actual crippled piece is in that damn binary blob the vendor
requires we use rather than documenting their configuration data.
Another reason to dislike having to use their tools: the hardware can
do things their tools have trouble with.
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