13 Nov
2011
13 Nov
'11
12:33 p.m.
On 11/12/2011 9:30 PM, Dave McGuire wrote:
On 11/13/2011 12:17 AM, Mouse wrote:
Works for Altera, too. I do it on Windows with cygwin. 'make generate' and then
load the programming file when done. I know I could probably setup the makefile
to do the steps only as needed, but I have not really found it to be worthwhile
(since most changes are to the verilog source, which requires a complete rebuild
anyway).
DESIGN=DE0_PDP8
TOOLS=/cygdrive/c/tools/altera/10.1sp1/quartus/bin
generate::
$(TOOLS)/quartus_map $(DESIGN) --write_settings_files=off
$(TOOLS)/quartus_fit $(DESIGN) --write_settings_files=off --seed=1
$(TOOLS)/quartus_asm $(DESIGN) --write_settings_files=off
$(TOOLS)/quartus_sta $(DESIGN)
$(TOOLS)/quartus_sta -t generate_timing.tcl $(DESIGN) 10
$(TOOLS)/quartus_eda $(DESIGN) --write_settings_files=off -c $(DESIGN)
$(TOOLS)/quartus_cpf -c $(DESIGN).cof
clean::
-rm -f $(DESIGN).*.rpt $(DESIGN).*.summary $(DESIGN).*.smsg $(DESIGN).map
$(DESIGN)_assignment_defaults.qdf TQ_*.rpt PLL*.txt
-rm -f $(DESIGN).done $(DESIGN).map $(DESIGN).pof $(DESIGN).sof
$(DESIGN).jic $(DESIGN).pin $(DESIGN).jdi $(DESIGN).qws $(DESIGN).*.ddb
-rm -rf db incremental_db simulation
# the end
I'm much less concerned about tools than I am
about documentation on
the hardware's interface, on what the bits in the blob thrown at the
hardware mean (and how to thrown them at it, though that part is much
more likely to be documented). I would probably find open-source tools
useful mainly as hardware documentation, though if they are properly
designed I might be able to pull off their UI and stick on something I
find usable.
The Xilinx FPGA tool suite, at least, can be driven from Makefiles. Fast,
efficient, predictable, automatable...very nice indeed. You don't HAVE to use
their bloated, lumbering IDE.
ra$ du -sh /usr/local/Xilinx
13G /usr/local/Xilinx
ra$
-Dave