17 Oct
2010
17 Oct
'10
7:06 p.m.
Does anyone have the ECO history of the pdp-8/i available? I am looking at
http://www.bitsavers.org/pdf/dec/pdp8/pdp8i/PDP8-I_CPU_blueprints_1969.pdf.
On sheet d-bs-8i-0-6 there's a gate added at D6 in the drawing, probably in
ECO #13, #25, or #50. It uses the M113 at F32N2 to invert something called
"IO PC LOAD", and connects to a previously tied high input of the 4-input
NAND at E32E2 (which calculates "PC LOAD").
The problem is, nothing anywhere in the drawings appears to generate a
signal
called "IO PC LOAD".
I don't imagine anyone knows off the top of their head what this signal is,
how it
is generated. A look at the ECO history should help explain when this was
added
and why, though.
Also, if anyone knows of an I/O device or option for the 8/i that would load
a new
value into the PC, that might give some clues where to look.
Thanks in advance,
Vince
(I am making excellent headway on a project which translate the 8/i
schematics,
including all the options, into Verilog for an FPGA, but I currently have
this signal
tied to an input pin for lack of any information about it.)
--
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18 Oct
18 Oct
5:26 p.m.
On Oct 17, 2010, at 7:06 PM, Vincent Slyngstad wrote:
(I am making excellent headway on a project which translate the 8/i schematics,
including all the options, into Verilog for an FPGA, but I currently have this signal
tied to an input pin for lack of any information about it.)
I realize it's not what you are doing, that is, I realize that what I did isn't
the same,
but I made an PDP-8/I clone in an FPGA, complete with the RF08 emulation and
all the time sharing options. I consulted the schematics but didn't follow them.
The only reason I mention it is that if when you done you want to boot TSS/8, I have
images, complete with sources which might be helpful. I would guess that at
some point you might want to try... (or maybe not, just a thought). I also have
tools to put together an RF08 disk "image" from the sources.
RF08 emulation with a IDE disk was fun in verilog :-)
-brad
Brad Parker
Heeltoe Consulting
781-483-3101
http://www.heeltoe.com
19 Oct
19 Oct
12:05 a.m.
From: Brad Parker; Monday, October 18, 2010 2:26 PM:
Yes, I was aware of your work. Yours is up and running, where mine is a
ways away,
yet :-).
(I am making
excellent headway on a project which translate the 8/i
schematics,
including all the options, into Verilog for an FPGA, but I currently have
this signal
tied to an input pin for lack of any information about it.)
I realize it's not what you are doing, that is, I realize that what I did
isn't the same,
but I made an PDP-8/I clone in an FPGA, complete with the RF08 emulation
and
all the time sharing options. I consulted the schematics but didn't
follow them. The only reason I mention it is that if when you done
you want to boot
TSS/8, I have
images, complete with sources which might be helpful. I would guess that
at
some point you might want to try... (or maybe not, just a thought). I
also have
tools to put together an RF08 disk "image" from the sources.
Thanks, I'll keep that in mind when I get that far.
RF08 emulation with a IDE disk was fun in verilog :-)
I bet :-).
Vince
20 Oct
20 Oct
7:11 a.m.
On 10/19/2010 12:05 AM, Vincent Slyngstad wrote:
Yes, I was aware of your work. Yours is up and running, where mine is
a ways away,
yet :-).
but your approach is aesthetically pleasing. I like it a lot.
But I wonder how much of the 8/I design depends on gate delays. From my
read of the schematics,
which I admit has been only cursory, there seemed to be a lot of "pulse
logic", which I worry about
in an FPGA. You should be able to simulate it, but it may be
interesting to see how that synthesizes.
*
*Still, worth doing, with a very cool result.
I think I might have an RF08 VPI model if you want one. It's simple but
it might give you a leg up.
(I still like the idea of a big PCB with lots of TTL which functions an
8/I. I'd buy one :-)
-brad
10:45 a.m.
From: "Brad Parker": Wednesday, October 20, 2010 4:11 AM
On 10/19/2010 12:05 AM, Vincent Slyngstad wrote:
Thanks! I'm hoping it continues to go well and will eventually work on
real hardware.
Yes, I was aware of your work. Yours is up and
running, where mine is a
ways away,
yet :-).
but your approach is aesthetically pleasing. I like it a lot. But I wonder how much of the 8/I design depends on
gate delays. From my
read of the schematics,
which I admit has been only cursory, there seemed to be a lot of "pulse
logic", which I worry about
in an FPGA. You should be able to simulate it, but it may be interesting
to see how that synthesizes.
I'm modeling the timing chains with shift registers for the delay lines,
with the shift registers driven synchronously by a master clock. The
toolset seems happy with that. The 8/I design is mostly set up with
TS[1234] being ended with TP[1234], so that the combinatorial logic
can settle before rising TPn triggers the latches. The FPGA tools seem
happy with all that.
Theoretically, it would be best to extract all the "clock-and"s from the
design, and put all the clock preconditions on the CE, rather than C
inputs to the latches (to minimize clock skew). I haven't done that, as
it would distort the relationship between the schematic and the Verilog
code quite a bit. My hope is that since the original design didn't need
it, that the FPGA version won't either.
There is one combinatorial loop in the design. Adder_l_ (the new value
for the link) depends on some stuff in the EAE, which in turn depends
on adder_l_. So I'm not sure what happens to link for certain operands
of the DIV instruction.
Other than that, what's done so far are the detailed Eagle schematics of
the 8/I backplane, some Perl to convert the netlist, pinlist, and partlist
to
Verilog, and the resultant Verilog, which compiles cleanly for synthesis.
There are several warnings about signals that are equivalent (bmb00_ and
mcbmb00_ are two copies of the same thing, for fanout). There are
also a couple of warnings about x_axis and y_axis, since there are no
D-A resources available internal to the FPGA to drive those (VC8I), and
a warning about latch inference for pwr_low_ (latch inference is the
intended result).
Next up, I am looking at issues with the pin-out, but if I multiplex the
front panel lights and also the switches, that should drop 90+ pins
from the pin-out, The plan is to add a hand-written
"top level", which
hooks up the MM8I emulation (block ram, already done),
and the various
"external" connections from the 8/I CPU core to the actual I/O
resources of the FPGA board.
I think I might have an RF08 VPI model if you want
one. It's simple but
it might give you a leg up.
Cool. I haven't used VPI before, but having a look couldn't hurt :-).
(I still like the idea of a big PCB with lots of TTL
which functions an
8/I. I'd buy one :-)
Hmm. I might choose the 8/L for something like that. Possibly soup
up the memory to 32K, but leave out all the option cruft of the 8/I
backplane. Otherwise you'd be looking at a mighty big board!
(I calculate about 4 feet on a side, to naively fold an 8/I backplane
flat.) Then again, the ratio of the 8/I to 8/L backplane sizes is about
2.5 to 1, so the board width (for a square board) would only be
about 1.6 to 1.
Vince
11:14 a.m.
On 10/20/10, Vincent Slyngstad <vrs at msn.com> wrote:
From: "Brad Parker": Wednesday, October 20,
2010 4:11 AM
And replace the 7453 and 7482 with something made with less unobtanium?
The memory extension hardware to take it over 4K is obviously
non-trivial in size (especially considering it doesn't fit in an -8/L
CPU enclosure). OTOH, if you have over 32K, there might as well be
provisions for OS/8-compatible mass storage, otherwise it's just a
papertape machine with more than 4K.
-ethan
(I still like the idea of a big PCB with lots of
TTL which functions an
8/I. I'd buy one :-)
Hmm. I might choose the 8/L for something like that. Possibly soup
up the memory to 32K, but leave out all the option cruft of the 8/I
backplane.
11:38 a.m.
From: "Ethan Dicks": Wednesday, October 20, 2010 8:14 AM
On 10/20/10, Vincent Slyngstad <vrs at msn.com>
wrote:
Sure. We've talked about how to do that before, I think. You'd face that
problem
starting from either the 8/I or the 8/L.
From: "Brad Parker": Wednesday, October
20, 2010 4:11 AM
And replace the 7453 and 7482 with something made with less unobtanium? (I still like the idea of a big PCB with lots of
TTL which functions an
8/I. I'd buy one :-)
Hmm. I might choose the 8/L for something like that. Possibly soup
up the memory to 32K, but leave out all the option cruft of the 8/I
backplane. The memory extension hardware to take it over 4K is
obviously
non-trivial in size (especially considering it doesn't fit in an -8/L
CPU enclosure).
Good point. You would definitely need some board area for that.
OTOH, if you have over 32K, there might as well be
provisions for OS/8-compatible mass storage, otherwise it's just a
papertape machine with more than 4K.
True, though an RF08 emulation doesn't take much board space. Or
one could go with an RX08 interface for extra clanking ambiance :-).
Vince
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