26 Jul
2015
26 Jul
'15
11:51 p.m.
I need to pick the brains of some PDP-8 experts. According to
the references I can find, especially the Small Computer Handbook,
the GTF instruction should include the M837 interrupt inhibit bit
in AC3. However, maindec 8E-D1HA test 05 seems to depend
on this not being true. Running the GTF instruction on my 8/M
when the inhibit FF is set results in a 0 in AC3. Furthermore,
both simh and Doug Jones' emulator omit the interrupt inhibit
bit in the GTF instruction. In fact Dr Jones' emulator has a /*?*/
comment in the code. Does anyone know the origin of this
discrepancy? Was the behavior the same on pre-Omnibus
versions of the 8, or did earlier address extensions include
that bit in the GTF result?
I came across this oddity in the course of writing an emulator
of my own, and I'd like understand what's going on here a little
deeper than "ignore the documentation, and make it work like
the real hardware."
Thanks in advance,
BLS
27 Jul
27 Jul
2:16 a.m.
From: Brian L. Stuart: Sunday, July 26, 2015 8:51 PM
I need to pick the brains of some PDP-8 experts.
According to
the references I can find, especially the Small Computer Handbook,
the GTF instruction should include the M837 interrupt inhibit bit
in AC3.
I can see where this happens in the M837 schematic (E50),
whenever DF is gated to AC9-11. That, in turn, seems to
be for GTF or RIB.
However, maindec 8E-D1HA test 05 seems to depend
on this not being true.
Can you tell us where you are seeing this? A pointer to the
copy of the diagnostic you're using, and perhaps an address?
There seem to be several GTF tests, if
http://svn.so-much-stuff.com/svn/trunk/pdp8/src/maindec/8e/d1ha-d.pdf
matches what you are running.
Running the GTF instruction on my 8/M
when the inhibit FF is set results in a 0 in AC3.
Curiouser.
Furthermore,
both simh and Doug Jones' emulator omit the interrupt inhibit
bit in the GTF instruction. In fact Dr Jones' emulator has a /*?*/
comment in the code. Does anyone know the origin of this
discrepancy? Was the behavior the same on pre-Omnibus
versions of the 8, or did earlier address extensions include
that bit in the GTF result?
I don't believe that the pre-Omnibus memory extensions
implement GTF.
The IM6100 datasheet says bits 3 and 5-11 are under control of
the memory extension. Reading the description for the IM6102,
it says GTF will place INT INH in AC3.
The HD6210 datasheet says bit 3 is the PWRON flag for GTF, and
bit 3 is unchanged by RIB.
The design of the KT8A is sufficiently opaque that I haven't figured
out yet how GTF works there.
Vince
5:39 a.m.
On 2015-07-27 08:16, Vincent Slyngstad wrote:
Correct. Pre-Omnibus machines had a rather different set of instructions
in in those opcodes.
From: Brian L. Stuart: Sunday, July 26, 2015 8:51 PM
To Stuart - are you sure your code does it right. Could you post it?
Running the GTF instruction on my 8/M
when the inhibit FF is set results in a 0 in AC3.
Curiouser. Furthermore,
both simh and Doug Jones' emulator omit the interrupt inhibit
bit in the GTF instruction. In fact Dr Jones' emulator has a /*?*/
comment in the code. Does anyone know the origin of this
discrepancy? Was the behavior the same on pre-Omnibus
versions of the 8, or did earlier address extensions include
that bit in the GTF result?
I don't believe that the pre-Omnibus memory extensions implement GTF. The IM6100 datasheet says bits 3 and 5-11 are under
control of the
memory extension. Reading the description for the IM6102, it says GTF
will place INT INH in AC3.
The HD6210 datasheet says bit 3 is the PWRON flag for GTF, and bit 3 is
unchanged by RIB.
The design of the KT8A is sufficiently opaque that I haven't figured out
yet how GTF works there.
he KT8A is very different. If someone is curious, the manuals do explain
it, or ask and I can try and explain it as well.
But essentially, AC3 in GTF in the KT8A is targeted for use to detect if
an IOT was executed while a delayed CIF was in effect in user mode.
Essentially saying to the OS that the user mode program is barfed and
cannot be restarted.
Johnny
--
Johnny Billquist || "I'm on a bus
|| on a psychedelic trip
email: bqt at softjar.se || Reading murder books
pdp is alive! || tryin' to stay hip" - B. Idol
11 a.m.
To Stuart - are you sure your code does it right.
Could you post it?
That's kind of what got me here. I was running the 8E-D1HA
maindec on my emulator and it was failing at that point. My
initial reaction was that I was misinterpreting the RTF behavior
and that perhaps it wasn't setting the interrupt inhibit as I
had thought. So I ran the diag on the real thing and single
stepped through that part. Sure enough the RTF does set it,
but GTF seems to not report it. That's when I got confused
enough to break down and look at other people's code :)
Here's my code for both the RTF and GTF instructions. Caveat:
it's in MCPL, but it should be close enough to C that it'll be
recognizable what's going on:
: 0, 0, 4 => // GTF
ac := link << 11 | irq() << 9 | ie << 7 | sf
// ac := link << 11 | irq() << 9 | ii << 8 | ie << 7 | sf
: 0, 0, 5 => // RTF
ie := 1
ii := 1
link := ac >> 11
ub := (ac >> 6) & #o1
ib := (ac >> 3) & #o7
df := ac & #o7
The line that's commented out on the GTF is the original version
I had where I did include the interrupt inhibit.
For comparison, here's the version in simh:
case 4: /* GTF */
LAC = (LAC & 010000) |
((LAC & 010000) >> 1) | (gtf << 10) |
(((int_req & INT_ALL) != 0) << 9) |
(((int_req & INT_ION) != 0) << 7) | SF;
break;
case 5: /* RTF */
gtf = ((LAC & 02000) >> 10);
UB = (LAC & 0100) >> 6;
IB = (LAC & 0070) << 9;
DF = (LAC & 0007) << 12;
LAC = ((LAC & 04000) << 1) | iot_data;
int_req = (int_req | INT_ION) & ~INT_NO_CIF_PENDING;
break;
and the one in Doug Jones' emulator:
case 04: /* GTF */
ac = (link >> 1) /* bit 0 */
#ifdef KE8E
| (gt?) /* bit 1 */
#endif
| ((irq > 0) << 9) /* bit 2 */
#ifdef KM8E
| (0) /*?*/ /* bit 3 */
#endif
| (enab << 7) /* bit 4 */
#ifdef KM8E
| sf /* bit 5-11 */
#endif
;
break;
case 05: /* RTF */
link = (ac<<1)& 010000; /* bit 0 */
#ifdef KE8E
gt = ? /* bit 1 */
#endif
/* nothing */ /* bit 2 */
/* nothing */ /* bit 3 */
enab = 1; /* bit 4 */
#ifdef KM8E
ub = (ac & 00100) >> 6; /* bit 5 */
ib = (ac & 00070) << 9; /* bit 6-8 */
dfr = (ac & 00007) << 12;/* bit 9-11 */
#endif
/* disable interrupts until branch */
enab_rtf = 0;
break;
BLS
10:48 a.m.
On Mon, 7/27/15, Vincent Slyngstad <v.slyngstad at frontier.com> wrote:
Interesting. By the time I got this far last night, I decided to put
off looking at the schematics to today. Thanks for the pointer.
It does indeed. In particular, in Test 05 on Page 35 of that PDF,
at address 2342, we load the AC with 5200, do an RTF, set the
AC to 7777, and then do a GTF and compare the result to 5200.
Although AC3 isn't set when executing the RTF instruction, one
of the effects of the RTF is to always set the interrupt inhibit. So
in my original code, the GTF resulted in a 5600, rather than a 5200.
Indeed. In trying to sort this out, I single stepped through this
part of the the maindec on my my actual machine making particular
note of the inhibit shown in the "no int" indicator in the status
switch setting. It does get set by the RTF, but after the GTF,
the accumulator has 5200 in it.
I need to pick
the brains of some PDP-8 experts.? According to
the references I can find, especially the Small Computer Handbook,
the GTF instruction should include the M837 interrupt inhibit bit
in AC3.
I can see where this happens in the M837 schematic (E50),
whenever DF is gated to AC9-11.? That, in turn, seems to
be for GTF or RIB. However,
maindec 8E-D1HA test 05 seems to depend
on this not being true.
Can you tell us where you are seeing this?? A pointer to the
copy of the diagnostic you're using, and perhaps an address?
There seem to be several GTF tests, if
http://svn.so-much-stuff.com/svn/trunk/pdp8/src/maindec/8e/d1ha-d.pdf
matches what you are running. Running the
GTF instruction on my 8/M
when the inhibit FF is set results in a 0 in AC3.
Curiouser. I don't believe that the pre-Omnibus memory
extensions
implement GTF.
Good point. As I was about to head to bed last night, I took a
look in the '67 small computer handbook and noticed that the
same instruction (6004) was used for a A/D converter in the
straight 8.
BLS
1 p.m.
I can see where this happens in the M837 schematic
(E50),
whenever DF is gated to AC9-11.? That, in turn, seems to
be for GTF or RIB.
I wonder if there are differences in different versions of the
schematics. If I'm reading the versions I got from bitsavers
correctly, on E50, Pins 2, 5, 11, and 14 are gated on to
DATA3, 9, 10, and 11 by a low on Pin 9. It looks like Pin 9
does identify the RIB and GTF instructions. But on this
version, it looks like Pin 2 is pulled high through R8. The
interrupt inhibit signal does come into Pin 1 which is gated
onto DATA3 by a low on Pin 7, and it's controlled by the
Omnibus IND signals for getting info to the front panel.
So it appears that these versions of the drawings agree
with the maindec and the observed behavior rather than
the documentation.
The versions I'm looking at appear to be for the Revs D
and E. Are the drawings you have that agree with the
documentation for an earlier rev, perhaps?
BLS
1:42 p.m.
From: Brian L. Stuart: Monday, July 27, 2015 10:00 AM
My drawings are for version D on revision C etch, but they
agree with yours on these connections. I was misreading
which signal went to pin 9 vs pin 7.
So it appears the KM8E does read a constant 0 for bit 3
during GTF (and RIB). This will apparently be different
everywhere else (DECmates, KT8A, etc.).
BTW, my replies have been bouncing from the Yahoo
groups, so you may want to forward stuff or otherwise
keep those folks in the loop.
Vince
I can see
where this happens in the M837 schematic (E50),
whenever DF is gated to AC9-11. That, in turn, seems to
be for GTF or RIB.
I wonder if there are differences in different versions of the
schematics. If I'm reading the versions I got from bitsavers
correctly, on E50, Pins 2, 5, 11, and 14 are gated on to
DATA3, 9, 10, and 11 by a low on Pin 9. It looks like Pin 9
does identify the RIB and GTF instructions. But on this
version, it looks like Pin 2 is pulled high through R8. The
interrupt inhibit signal does come into Pin 1 which is gated
onto DATA3 by a low on Pin 7, and it's controlled by the
Omnibus IND signals for getting info to the front panel.
So it appears that these versions of the drawings agree
with the maindec and the observed behavior rather than
the documentation.
The versions I'm looking at appear to be for the Revs D
and E. Are the drawings you have that agree with the
documentation for an earlier rev, perhaps?
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blstuart＠bellsouth.net -
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v.slyngstad＠frontier.com