Reproducing old machines with newer technology (Re: PDP-12 at the RICM)

tony duell ard at
Wed Jul 15 00:21:39 CDT 2015

> > My experience of FPGAs is that if you design a circuit for an FPGA it will work. If you take an existing design
> > feed it into a schematic capture program and compile it for an FPGA then it won't.
> Actually, you can, and I have done so - provided that the original
> machine was slow enough.  It works, in part, because the FPGA's are
> sooooooooooo much faster than the original design, that you can use the
> "trailing D flip flop" approach I described to convert the former into
> the latter - the glitches occur on the time scale of the FPGA logic, but
> are gone by the time the next simulated machine clock arrives.

That is not 'taking an existing design and feeding it into a schematic capture program'. It's modifying the
design (adding the D-types to synchronise signals and removed glitches). I do not dispute you can do that.


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