Reproducing old machines with newer technology (Re: PDP-12 at the RICM)

Jay Jaeger cube1 at
Wed Jul 15 21:11:58 CDT 2015

This brings up a good point:  just because a D Flip Flop is clocked by
something other than a system-wide (or subsystem-wide) clock does not
turn it into a latch.  Flip flops can clocked by combinatorial inputs.
This can be a problematic thing of course, as they can cause glitch
problems - had a couple of those in our student-designed 12 bit
computer, where I ended up feeding the combinatorial input into a D Flip
flop that was clocked by the FPGA-wide 50 Mhz clock, and then fed the
output of that to the flip flops (in my case JK rather than D, but the
idea would be the same).


On 7/15/2015 9:02 PM, Jon Elson wrote:
> On 07/15/2015 01:24 PM, Noel Chiappa wrote:
>>      > On 7/14/2015 7:36 PM, Jon Elson wrote:
>>      > On the system 360 CPUs, they did not use flip-flops like we are
>> used
>>      > to, today. They used latches ... Since these were discrete
>> transistor
>>      > implementations, a real flip-flop was too expensive, but a
>> latch could
>>      > be implemented in about 6 transistors, I think.
>>      > The 11/45 used TTL ICs, so real FFs were available in that
>> technology,
>>      > although they may have used latches as well.
>> This confused me a bit, until I realized that you were using "latch"
>> for what
>> I think of as 'SR flip-flop', and "flip-flop" for 'D and JK flip-flops'.
>> Guess that shows how long ago I did hardware... :-)
>> To be a bit more detailed, on the 360's, were those latches 'simple'
>> SR flops
>> (i.e. un-gated), or were they gated?
> Well, one would have to dig into the ALDs to be sure.  But, the FEMMs
> have some large drawings that are essentially RTL in graphical form, and
> a lot of description of how it all worked.  My understanding is all
> those registers were essentially D latches. So, they got one data input
> from the ALU or a mux, and a latch pulse, and provided a Q output.  Each
> of these latches took up at least 4 SLT packages, I'm not sure exactly
> how many for sure.  So, the whole latch was composed of something like 4
> NOR gates or the equivalent, plus one inverter.
> (Sorry about being so vague, I read a bunch of IBM FEMMs about a year
> ago when I had some spare time.)
> Jon

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