KT-24 and/or -11/24 backplane info
jnc at mercury.lcs.mit.edu
Sun Jul 24 08:11:00 CDT 2016
> Guess I should document all this in the Computer History Wiki
> those prints (KT-24, and -11/24 backplane) would still be useful.
Big thanks for Al for putting the KT24 prints up - very good to have them.
> I guess it will require getting ahold of a backplane, and seeing what I
> can find out with an ohm-meter.
It looks like I'll still have to do this at some point, to confirm my
theories about how the two busses are wired on the backplane (separation of
UB and EUB address lines, and cross-connection of the data lines, for the
EUB/SPC slots), since we still don't have any backplane info.
Another mystery: The "PDP-11 UNIBUS Processor Handbook" (1985) says (pg. 4-10)
that in the 5.25" box, "only one MS11-P memory module can be
configured". Anyone know the cause/source of that restriction?
I don't think it can be the backplane; i) AFAIK, the 5.25" and 10.5" (for
which no limitation is stated) boxes use the same backplane, and ii) the 5.25"
box can take more of the smaller MS11-L cards (albeit, again, limited - to
three). So I don't think it can be 'the backplane doesn't carry all 22 address
lines to all EUB slots' (although I will check); and the CPU does drive all
My next thought was that it's some power supply current issue, but on
checking, that board only uses +5V, and there's nothing about limiting the
number of ordinary boards when an MS11-P is in use. (I have to check the power
supply specs, and compare with the board power consumption specs, to make
completely positive there's no issue there.)
So I can't come up with any technical rationale for that limit? Am I missing
something? Or is it just DEC marketing, trying to limit how powerful the
machine can be?
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