How do they make Verilog code for unknown ICs?

ben bfranchuk at
Mon Jun 20 16:01:46 CDT 2016

On 6/20/2016 2:24 PM, Ian Finder wrote:
> I find most of the open source HDL simulators kind of suck. I think you can
> still get ModelSim Web edition for free from altera.

I think you get 1 month free ... then $$$.

I like the CRASH and BURN testing for FPGA's.
What I want is 5 volt I/O FPGA with a flash Boot prom for the FPGA
on tiny 64 pin PCB. This way one can emulate a vintage logic board
or cpu.

> This will do mixed language designs of Verilog, VHDL and schematic, and
> works rather nicely.

Altera has AHDL as well. Not portable, but less confusing to write logic

> Remember, each module is just a set of input and output signals, so the
> language really doesn't matter. Mixed language designs are very common.
> Yes, you can even build FPGA designs in a schematic editor out of library
> modules. No, I don't suggest you should.

With Altera, you had a TTL macro library at one time. Not sure if the 
newest version still supports it.


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