Fwd: Re: DEC bus transceivers
aek at bitsavers.org
Mon Oct 24 13:09:20 CDT 2016
-------- Forwarded Message --------
Subject: Re: DEC bus transceivers
Date: Mon, 24 Oct 2016 13:37:14 -0400
From: allison <ajp166 at verizon.net>
Reply-To: General Discussion: On-Topic Posts <cctech at classiccmp.org>
To: General Discussion: On-Topic Posts <cctech at classiccmp.org>
On 10/23/16 2:59 PM, Al Kossow wrote:
> On 10/23/16 11:50 AM, shadoooo wrote:
>> The problem is that there aren't open drain bus transceivers, but the
>> problem could be solved simply using input-only and output-only components,
>> connecting two in parallel but opposite direction on bidirectional pins.
> The reason for using the old parts is the logic thresholds are unique to
> the Unibus to handle worst-case bus loading and the termination voltage they
The voltages are based on TTL levels. What are the unique voltages?
The key was limited leakage current and input current to not load the bus by inserting or removing
current from a node (there is a specified maximum in per node and total nodes). That cover input
to card devices and bus driver leakage.
Logic low voltage is typical of TTL and the driver device has to sink that current and meet that value.
Logic High was set by the terminator devices at 3.36V but the threshold is lower based on the bus
By late 1970 it was an easy spec to meet, When first used (pdp8e) it was new and the ICs
were not so great with leakage current and output device saturation current.
Every time this comes up the world is supposed to stop if not met. The LSI-11 bus (qbus)
was actually harder as it was 120 ohm terminated and HeathKit did it with common TTL
and the CPU was DEC standard LSI-11 and it worked out to 18 slot backplanes.
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